1. Field of the Invention
The present invention relates to a method for manufacturing a packaging structure, and more particularly, to a method for manufacturing a chip packaging structure.
2. Descriptions of the Related Art
There are many kinds of chip packaging structures, one of which generally comprises a chip and a substrate. The chip is placed on the substrate, pads of the chip are electrically connected with a circuit of the substrate, and the chip and the substrate are optionally further encapsulated by an encapsulation. Such a chip packaging structure is disclosed in U.S. Pat. No. 7,919,851.
The aforesaid chip packaging structure has been developed for many years, so the technologies thereof are much mature and the yield is high. However, the substrate of the chip packaging structure is formed by stacking a plurality of layers of materials and thus has a larger thickness, so it is difficult to reduce the overall thickness of the chip packaging structure to a desired value. As electronic products are developing toward a thinner profile, applications of such chip packaging structures having a large thickness will be limited.
In view of this, an urgent need exists in the art to provide a method for manufacturing a chip packaging structure which can overcome at least one of the aforesaid shortcomings.